Channel selection arbitration

ABSTRACT

A system for arbitration between competeting channels in, for example, a direct memory access (DMA) controller is described. The system arbitrates much more fairly than in the traditional `round robin` approach, especially when channel requests are not independent but instead are made and withdrawn simultaneously by groups of channels. A `turn-taken` latch is defined, and is consulted when a channel selection is made. This latch is set when a channel is serviced, and priority is given to requesting channel for which the latch is not set. When the latch is set for all of the requesting channels, an arbitrary winner is selected and the latch is reset for all except the winning channel.

BACKGROUND OF THE INVENTION

The present invention relates to a circuit and method for arbitrationbetween channels competing for selection, and to a data processingsystem employing such a circuit.

It is common for electronic devices to be connected to a number ofperipheral devices, or channels, and to select one channel for servicingat any one time. An example of this is found in the field of directmemory access (DMA) data transfer in a computer system, in which data istransferred by a number of different `slave` devices, or channels,primarily to and from the main memory, without using the centralprocessing unit (CPU). Typically a DMA controller is used to superviseand control these data transfers. Bypassing the CPU usually allowshigher data transfer rates and also frees the CPU for other processingtasks.

In a system in which a number of peripheral devices compete for use of asingle DMA data bus, the DMA controller must arbitrate betweensimultaneously received DMA requests, granting one channel the use ofthe DMA data bus at any one time. This arbitration should be performedin a `fair` way, so that each requesting device is allocated areasonable share of the use of the data bus.

A further complication arises when the DMA channels are arranged torequest access to the DMA data bus in groups, rather than independently.This may occur, for example, when a number of DMA channels are arrangedto transmit data on a single bus or along a single cable in apacket-multiplexed manner. In this case, requests from all the channelswithin the group will be received simultaneously, and all of theserequests will be removed when any of the channels within the group isservice. There will be a pause while the packet is transmitted, and thenall of the channels in that group will request again. The DMA controllermust allocate bus usage fairly within each group, as well as betweengroups.

One prior art request arbitration method is the so-called `rotatingpriority` or `round robin` approach, as used in several commerciallyavailable DMA controllers such as the Motorola MC6844 (described in`Motorola Microprocessor, Microcontroller and Peripheral Data, VolumeII`, 1988 pages 3-1757 to 3-1773) and the Intel 8237A and 8257A(described in `Intel Microsystem Components Handbook--Microprocessorsand Peripherals` Volume 1, pages 2-61 to 2-88). In this system eachchannel is assigned a priority value. At any time the requesting channelhaving the highest priority is allowed access to the DMA data bus; thatchannel is then assigned the lowest possible priority, and the priorityof each of the other channels is incremented. The next DMA access isgiven to the new highest priority requesting channel.

The rotating priority scheme works well when the requesting channels areall independent, but does not provide fair arbitration between competingrequests when the channels are organised into groups. In this lattersituation, requests by some of the channels may never be serviced. Thisproblem will be described further below with reference to certain of theaccompanying drawings.

Another prior art arbitration scheme is described in GB 2202977, inwhich the channels transmit a priority value to a DMA controller on aseparate arbitration bus. The controller then compares this value withone stored within the controller before deciding whether to grant DMAaccess to that channel.

SUMMARY OF THE INVENTION

According to the present invention on there is provided an arbitrationcircuit for selecting a winning channel from a plurality of channelsrequesting selection, comprising: a memory element corresponding to eachchannel; first logic means for determining whether the memory elementfor any of the requesting channels is in a first state; and secondlogic, means responsive to a positive determination by the first logicmeans, for selecting as winner one of the requesting channels for whichthe memory element is in said first state, and for setting the memoryelement corresponding to the winning channel to a second state.

An arbitration circuit according to the invention solves the problemsdescribed above by providing a fair arbitration both within and betweengroups of simultaneously requesting channels. When a particular channelis selected, or serviced, the memory element corresponding to thatchannel is set to the second state. In the broadest aspect of theinvention, such a channel would then not be considered for subsequentselection.

In order that a selection can be made when all of the requestingchannels have been serviced, the arbitration circuit: preferablyincludes third logic means, responsive to a negative determination bythe first logic means, for selecting as winner one of the requestingchannels, and for setting the memory element corresponding to eachrequesting channel except the winning channel to the first state.

Although the second and third logic means could select a winning channelfrom the appropriate group of eligible channels by a random decision, itis preferred that this selection be made according to a predeterminedorder of priority between the channels. It is further desirable that thesecond and third logic means include means for preventing the selectionof more than one requesting channel as winner.

In a preferred embodiment, the arbitration circuit is arranged as aplurality of interlinked sub-circuits, each sub-circuit corresponding toa single channel and including the memory element corresponding to thatchannel. This allows the circuit to be designed and constructed in amodular manner.

Although any sort of register or latch could be used, it is preferredthat the memory element is a set-dominant set-reset (RS) latch.

Viewed from a second aspect the present invention also provides a dataprocessing system including a direct memory access (DMA) controllercomprising an arbitration circuit according to the invention, andfurther comprising: at least one memory device; at least one datahandling device; and interconnecting buses; wherein DMA transfers can bemade between the memory device(s) and the data handling device(s) viathe DMA controller.

Viewed from a third aspect the invention further provides a method ofselecting a winning channel from a plurality of channels requestingselection, wherein a memory element associated with each channel can beset to one of at least two states, comprising the steps of: determiningwhether the memory element corresponding to any of the requestingchannels is in a first state; and, if so, selecting as winner one of therequesting channels for which the memory element is in the first state,and setting the memory element corresponding to the winner to a secondstate.

BRIEF DESCRIPTION OF THE DRAWINGS

In order that the invention may be fully understood a preferredembodiment thereof will now be described, by way of example only, withreference to the accompanying drawings in which:

FIG. 1 shows a block diagram o;f an arbitration circuit as known in theprior art;

FIG. 2 shows schematically the use of the rotating priority scheme in asystem comprising four channels independently requesting selection;

FIG. 3 shows schematically the use of the rotating priority scheme in asystem comprising two groups of two channels requesting selection;

FIG. 4 shows schematically tile operation of an arbitration circuitaccording to the invention;

FIG. 5 shows a logic circuit diagram for one channel of an arbitrationcircuit according to the invention; and

FIG. 6 shows a computer system in which an arbitration circuit accordingto the invention is incorporated in a DMA control device.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring now to FIG. 1 an arbitration circuit 100, as known in theprior art, receives selection requests 110 from a number of channels(not shown). The arbitration circuit 100 selects a channel to beserviced (the `winner`) and indicates the identity of the winner onoutput 120. When the winning channel is serviced a pulse is applied tothe update input 130 of the arbitration circuit, to indicate that anarbitration cycle is complete and the arbitration circuit should nowevaluate the next winning channel according to its current requests 110.

When more than one request input 110 is active, the winners inconsecutive cycles should be selected in a fair manner, so that over alarge number of cycles each requesting channel is the winner for areasonable number of cycles.

FIG. 2 shows the use of the prior art `rotating priority` system in thecase of four independently requesting channels 1,2,3 and 4. In thefigure, an `R` indicates that that channel is currently requestingselection. In each cycle, the highest priority channel is shown at thetop of the figure. At the beginning of the first cycle, cycle (a), thechannels are assigned arbitrary priority values, with channel 1 havingthe highest initial priority.

Throughout FIG. 2, only three of the channels 1,3 and 4 are shown makingrequests to the arbitration circuit. Accordingly in cycle (a) channel 1is the highest priority of those requesting service, and so becomes thewinner. In cycle (b) the winner from cycle (a) becomes the lowestpriority channel, and the highest priority requesting channel (thewinner) is channel 3. Similarly, in cycle (c) the priorities rotate sothat channel 4 is the highest priority requesting channel, and so on.

In the situation shown in FIG. 2, the rotating priority arbitrationscheme provides a fair arbitration between the requesting channels, inthat each channel in turn becomes the highest priority channel, andtherefore the winner for that cycle. However the same scheme applied tochannels organised in groups does not lead to fair arbitration; thiswill be demonstrated below with reference to FIG. 3.

FIG. 3 shows schematically the use of the rotating priority scheme in asystem comprising two groups of two channels requesting selection. Inparticular, channels 1 and 2 request together, and channels 3 and 4request together. When an individual channel is serviced, all members ofits group stop requesting, and reissue requests in time for the nextcycle.

As in FIG. 2, in FIG. 3 the channels have been assigned an arbitraryorder of priority at the start of cycle (a). In that cycle both groupsof channels make requests, and channel 1 is serviced as the highestpriority requesting channel. In time for cycle (b), channel 1 isassigned the lowest priority, while the priorities of the other channelsare all incremented. In cycle (b) the group comprising channels 3 and 4makes a request, and channel 3 becomes the winner. In cycle (c) thegroup comprising channels 1 and 2 requests, and channel 1 is made thewinner. In cycle (d) channel 3 is again the winner.

It will be seen that in the situation shown in FIG. 3, in which thechannel groups make requests on alternate cycles, the arbitration is farfrom being fair. In the example shown, while channels 1 and 3 areregularly serviced, channels 2 and 4 are never serviced.

An arbitration scheme according to the invention will now be described,with reference to FIGS. 4 and 5. The basis of the scheme is a`turn-taken` latch or memory element (230, FIG. 5) corresponding to eachchannel, which is clocked at each arbitration cycle. From the state ofthis latch a fair arbitration decision can be made to decide which ofthe requesting channels should next be serviced.

Arbitration proceeds as follows:

1) For each channel, define a binary control value:

PENDING=REQUESTING AND (NOT TURN₋₋ TAKEN)

2) Select one of the channels for which PENDING is set (for example, thelowest numbered channel) and service it.

Set TURN₋₋ TAKEN latch for the channel serviced.

3) If no PENDING bits are set, but one or more channels are requesting(in other words, each requesting channel has had a turn), then:

reset TURN₋₋ TAKEN for each channel which is REQUESTING; and

redefine PENDING=REQUESTING

The operation of this arbitration scheme is shown in FIG. 4, in whicharbitration between channels numbered 1 to 4 is considered. In thisfigure the channels are organised as two groups of two (1,2); (3,4). An`R` by the channel number indicates that that channel is currentlyrequesting service--that is to say, its REQUESTING bit is set.Similarly, a `T` indicates that the TURN₋₋ TAKEN latch for that channelis set. Seven arbitration cycles, (a) to (g), are shown.

Referring to FIG. 4, all of the channels are requesting in cycle (a),but none of them has the TURN₋₋ TAKEN latch set. Therefore the PENDINGbit is a logical `1` for each channel, and an arbitrary channel (in thiscase channel number 1, the lowest numbered channel) is selected forservicing. TURN₋₋ TAKEN for channel 1 is then set.

In cycle (b) channels 3 and 4 are requesting, and again the lowestnumbered channel (channel 3) is selected because, at the time ofselection, neither has its TURN₋₋ TAKEN latch set. As a result of itssuccessful selection channel 3 then has its TURN₋₋ TAKEN latch set.

In cycle (c) channels 1 and 2 again make requests. From above, thebinary value PENDING is calculated:

PENDING=REQUESTING AND (NOT TURN₋₋ TAKEN)

=1 AND 0=0 for channel 1;

=1 AND 1=1 for channel 2; and

=0 for channels 3 and 4 (for which REQUESTING=0)

Therefore channel 2 is the only PENDING channel, and is therefore thewinner. Its TURN₋₋ TAKEN latch ]s then set.

The situation is similar in cycle (d) in which channel 4 is the onlyrequesting channel for which PENDING is a logical `1` and is thereforeselected.

So far, in cycles (a) to (d), it has been possible to select aREQUESTING channel for which TURN₋₋ TAKEN is not set--in other words, achannel for which the value

PENDING=REQUESTING AND (NOT TURN₋₋ TAKEN)

=`1`.

However, this is no longer possible in cycle (e), so the third step fromthe scheme above is required:

3) If no PENDING bits are set, but one or more channels are requesting(in other words, each requesting channel has had a turn), then:

reset TURN₋₋ TAKEN for each channel which is REQUESTING; and

redefine PENDING=REQUESTING

Applying this step to cycle (e), channels 1 and 2 are REQUESTING, soboth have a PENDING value of 1 by this new, temporary, definition.Accordingly, channel 1 is selected as the lowest numbered of the PENDINGchannels. TURN₋₋ TAKEN is reset for all REQUESTING channels, but in factis set again for channel 1 to show that this channel has been the winnerin that cycle.

The situation in cycle (f) is similar, in which both channels 3 and 4are REQUESTING, but both have their TURN₋₋ TAKEN latches set. Similarreasoning to that used in connection with cycle (e) results in channel 3being selected.

In the final example, cycle (g), channels 1 and 2 are REQUESTING.According to the original definition of PENDING,

PENDING=REQUESTING AND (NOT TURN₋₋ TAKEN),

the PENDING bit is set for channel 2. It is therefore not necessary torely on the arrangements in the third step of the scheme above, andchannel 2 is selected in the normal manner.

FIG. 5 shows a logic circuit diagram for one channel 200 of anarbitration circuit according to the invention. The circuitry shownbetween the dashed lines is repeated for each channel. Requests forselection are received as a logical `1` on the REQUEST input 210, and anindication that that channel is the winner of the arbitration during aparticular cycle is provided by a logical `1` on the WON output 220.

The TURN₋₋ TAKEN latch 230 is a set-dominant set-reset (RS) latch, andis provided with suitable clocking pulses (not shown) from the UPDATEinput 130 in FIG. 1. Its output 260 represents the value TURN₋₋ TAKEN.

The value PENDING is determined by AND gate 340, the output of which isequal to

REQUESTING (NOT TURN₋₋ TAKEN)

except under circumstances when no REQUESTING channels have theirPENDING bit set (see below and step (3) above). It should be noted thatan open circle on the input or output of a logic gate in FIG. 5 denotesa logical inversion of that input or output.

Logic gate 300 also produces a logical `1` as its output when REQUESTINGis set but TURN₋₋ TAKEN is not (that is, PENDING=`1` according to thefirst definition). The output from gate 300 and the equivalent gates inall of the other channels form inputs to NOR gate 310. Accordingly, theoutput of NOR gate 310 is a logical `1` only when all of its inputs arezero--that is, when no REQUESTING channel has its PENDING bit set. Underthese circumstances only, the TURN₋₋ TAKEN latch is overidden by meansof a logical `1` Applied to OR gate 330. This corresponds to the thirdstep in the scheme described above, in which PENDING is temporarilyredefined as being equal to REQUESTING. Also, a logical `1` is applied(via AN gate 320) to the R (reset) input 240 of the latch 230 for eachREQUESTING channel. These latches will be reset on the next clock(UPDATE) pulse applied.

Returning to gate 340, it will now:be seen that the output of this gaterepresents the value PENDING according to either of its two definitionsgiven above. That is to say, PENDING normally equals

REQUESTING AND (NOT TURN₋₋ TAKEN),

but when no REQUESTING channel has its PENDING bit set according to thisfirst definition, PENDING is temporarily redefined as being equal toREQUESTING. Whichever definition is in force, PENDING is provided bygate 340.

One of the channels for which PENDING is set must now be selected aswinner. In the example shown in FIG. 4, the lowest numbered PENDINGchannel was chosen as the winner. In the implementation shown in FIG. 5,gates 350 and 360 are used to achieve this predetermined but arbitraryselection between PENDING channels.

Gate 350 derives the logical value

WON=PENDING AND (NOT PREVIOUS),

where PREVIOUS is the input on line 370. It will therefore be clear thatin order for a particular PENDING channel to be selected as the winner,the value of PREVIOUS received by that channel on input 370 must be alogical `0`. For the particular winning channel selected, the outputNEXT on output 380 will always be a logical `1`. Similarly, for achannel which is not PENDING, the output NEXT 380 will equal (PREVIOUSOR `0`)=PREVIOUS. The output NEXT 380 for each channel (except the last)is connected to the input PREVIOUS 370 for the subsequent channel.

The effect of gates 350 and 360 is therefore as follows:

a) For a channel to win, its PREVIOUS input 370 must be a logical `0 `;

b) If any channel wins then its output NEXT 380 to the next channel willbe a logical `1`;

c) If the PREVIOUS input to a channel is a logical `1` then thatchannel's NEXT output 380 will automatically be a logical `1`.

Given that a channel must have its PENDING bit set (by either of theabove definitions) in order to be the winner, it will now be clear thatthe first PENDING channel in the chain of NEXT 380 to PREVIOUS 370connections will be selected as the winner. Any channels further on inthe chain will receive a logical `1` on their PREVIOUS input 370, andwill therefore be prevented from being the winner. As a result, in thisembodiment, there can only be one winner.

The output WON 220 for each channel is also connected to the S (set)input 250 of latch 230. The effect of this is that the TURN₋₋ TAKENlatch is always set for the winning channel when the clock or UPDATEpulse is applied.

FIG. 6 shows a computer system in which an arbitration circuit accordingto the invention is incorporated in a DMA control device 500. Theparticular system shown is suitable for use as the control circuitry fora data storage subsystem comprising four DASDs or disk drives 610. Inthis system DMA transfers are required in both directions between theDASDs 610 and the buffer DRAM 540, and also in both directions betweenthe buffer DRAM 540 and the adapters 620 (through which the storagesubsystem communicates with its host (controlling) data processor).

The device 500 performs the functions of a DMA controller and, in thiscase, a general system control let, operating in this latter respectunder the control of program code stored in the EPROM 520 and static RAM510, both of which are connected t:o controller 500 via the CS (ControlStore) bus 530.

The need for an arbitration circuit in the DMA controller 500 arisesbecause each of the DASDs 610 includes 2 DMA channels, which can makerequests as groups, the adapter has 4 DMA channels, and the DMAcontroller 500 has 3 internal DMA channels for internal transfers. Eachof the 16 non-internal DMA channels can make requests via the DMA bus630 and, if selected for a particular cycle, transfers a small packet ofdata via bus 630 and controller link chips 600.

Although the invention has been described with reference to anembodiment employing discrete logic gates, it will be clear thatintegrated circuit embodiments could easily be used. In addition, theinvention could be implemented as a general purpose logic device, suchas a microprocessor, under control of a computer program.

I claim as my invention:
 1. Arbitration apparatus for selecting awinning channel from a plurality of channels requesting selection, saidarbitration apparatus comprising:a separate REQUEST input line for eachchannel, indicating that said each channel is requesting service; aseparate WON output line for each channel, indicating that one of saidchannels is said winning channel; a separate circuit for each of saidchannels, each said separate circuit includingTURN₋₋ TAKEN memory meanshaving an S state set when the WON output line for its own channel isactive, and having an R state set either when both (a) said REQUEST linefor its own channel is active and a PENDING signal for its own channelis active or (b) when no other channel has a PENDING signal active;first logic means for producing a PENDING signal when (a) its ownREQUEST line is active and state R is set or when (b) said S state isset and no other of said separate circuits has its PENDING signalactive; and second logic means for producing said WON signal on theoutput line of its own channel when both (a) said PENDING signal isactive and (b) no WON signal from another channel is active.
 2. Thearbitration apparatus of claim: 1, further includingthird logic meansfor ordering each of said separate circuits in a priority order when thePENDING signal of more than one of said circuits is active.
 3. Thearbitration means of claim 2, wherein said third logic means of each ofsaid circuits receives a PREVIOUS signal from a first other of saidcircuits and produces a NEXT signal coupled to the PREVIOUS signal of asecond other of said circuits, for ordering said circuits in saidpriority.
 4. The arbitration apparatus of claim 1, wherein said memorymeans sets said S state in the presence of said WON signal regardless ofthe state of its own REQUEST line.
 5. A data processing system includinga direct memory access (DMA) controller (500) comprising an arbitrationapparatus as claimed in any preceding claim, said system furthercomprising:at least one memory device; at least one data handlingdevice; and at least one interconnecting bus; wherein said memory deviceis coupled to channels in said data handling device via said DMAcontroller for DMA transfers between said memory device and saidchannels.
 6. A method of selecting a winning channel from a plurality ofchannels requesting selection, each of said channels having a separateREQUEST input line indicating that said each channel is requestingservice, and each of said channels having a separate WON output lineindicating whether said each channel is said winning channel, saidmethod comprising performing the following steps for each of saidchannels:setting an S state set when the WON output line for its ownchannel is active, and setting an R state set either when (a) saidREQUEST line for its own channel is active and a PENDING signal for itsown channel is active or (b) when no other channel of said plurality ofchannels has a PENDING signal active; producing a PENDING signal when(a) said each channel's own REQUEST line is active and state R is set,or (b) said S state is set and no other of said channels has its PENDINGsignal active; and producing said WON signal on said each channel's ownWON line when both (a) said PENDING signal is active and (b) no WONsignal from another channel is active.